![]() ![]() The direct control signal is connected to one input of the ‘G4’, ‘G5’ & ‘G6’ and one more input of the ‘G4’, ‘G5’ & ‘G6’ are connected to the outputs of Flip Flops like QA, QB, and QC. Here, ‘A’ is directly connected to DA of the first flip flop. After that, NOT gate outputs are connected to ‘G1’, ‘G2’, and ‘G3’, and the other inputs of G1, G2 & G3 are B, C & D. One control signal (Shift/Load) is used to control the parallel input and serial output. In this parallel input serial output (PISO) shift register circuit, logic gates are used. Here, one CLK pulse is enough to load the 4-bit of data but four pulses are required to unload all the four bits. After that, it is read out from the shift register serially 1-bit at a time from input pins on every CLK cycle. In the above-shown PISO shift register circuit, the input data is applied to the input pins of the shift registers from D A to D D at the same time. PISO Shift Register Circuit PISO Shift Register Working So the FFs in the circuit are synchronous through each other because a similar CLK signal is given to every flip flop. ![]() The previous FF’s o/p, as well as parallel input data, is simply connected to the i/p of the second flip flop. ![]()
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